3d历史试机号833the ft34c04a is a 1.7v rated minimum operating voltage serial eeprom device containing 4096-bits of serially electrically erasable and programmable read-only memory (eeprom) organized as 512-bytes of eight bits each. the serial eeprom operation is tailored specifically for dram memory modules with serial presence detect (spd) to store a module’s vital product data such as the module’s size, speed, voltage, data width, and timing parameters.the ft34c04a is protocol compatible with the legacy jedec ee1002 specification (2-kbit) devices enabling the ft34c04a to be utilized in legacy applications without any software changes. the device is designed to respond to specific software commands that allow users to identify and set which half of the memory the internal address counter is located. this special page addressing method to select the upper or lower half of the serial eeprom is what facilitates legacy compatibility. however, there is one exception to the legacy compatibility as the ft34c04a does not support the permanent write protection feature.additionally, the ft34c04a incorporates a reversible software write protection (rswp) feature enabling the capability to selectively write protect any or all of the four 128-byte quadrants. once the rswp is set, it can only be reversed by sending a specific software command sequence.the ft34c04a supports the industry standard 2-wire i2c fast-mode plus (fm+) serial interface allowing device communication to operate at up to 1mhz. a bus timeout feature is supported to help prevent system lock-ups. the ft34c04a is available in space saving sop, tssop, and udfn packages.
low voltage and low power operations:
ft34c04a: vcc = 1.7v to 3.6v, industrial temperature range (-40℃ to 85℃).
jedec jc42.4 (ee1004-v) serial presence detect (spd) compliant
individually reversible software write protection on all four 128-byte quadrants.
16 bytes page write mode.
partial page write operation allowed.
industy standard 100khz, 400 khz,and 1mhz i2c interface.
schmitt trigger, filtered inputs for noise protection.
3d历史试机号833self-timed programming cycle (5ms maximum).
bus timeout supported
3d历史试机号833automatic erase before write operation.
high reliability: typically 1,000,000 cycles endurance.
3d历史试机号833100 years data retention.
standard 8-lead jedec sop, 8-lead tssop, and 8-pad udfn pb-free packages.查看详情